module pulse_counter(
    input clk,
    input rst,
    input pulse,        // 消抖后脉冲
    output reg [3:0] count // 0-9计数值
);
always @(posedge clk or posedge rst) begin
    if (rst) count <= 0;
    else if (pulse) count <= (count == 9) ? 0 : count + 1;
end
endmodule